Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive respective word lines, and sector switches provided one for each sector. The sector switches are connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation. The sector switches only include transistors directly connected to an output signal line to provide the negative voltage to the word line drivers. A decoding circuit shared by one or more sectors is adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. continuation application filed under 35 USC111(a) claiming benefit under 35 USC 120 and 365(c) of PCT applicationJP2003/004921, filed on Apr. 17, 2003, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a nonvolatile semiconductormemory device, and particularly relates to a nonvolatile semiconductormemory device adapted to erase data on a whole sector at a time.

2. Description of the Related Art

Nonvolatile semiconductor memory devices are designed to write data by aprogramming operation of injecting charges into a gate of a memory celltransistor, and to erase data by an erasing operation of removingcharges from the gate of the memory cell transistor. The programming anderasing operations are executed by applying a voltage predetermined foreach operation to respective terminals of the gate, the drain and thesource of the memory cell transistor. The predetermined voltage must bea voltage higher than an external supply voltage supplied from theoutside or a negative voltage lower than a ground voltage. Thenonvolatile semiconductor memory devices therefore include internalprogram voltage and erase voltage generating circuits to generate a highvoltage and a negative voltage.

In word line voltage control, the high voltage for programming generatedby the program voltage generating circuit is applied to a selected wordline in a selected sector via an X-decoder circuit. The negative voltagefor erasure generated by the erase voltage generating circuit is appliedto word lines in a selected sector via the X-decoder circuit.

FIG. 1 is a schematic diagram of an X-decoder circuit. This X-decodercircuit is provided one for each block. If there are plural blocks, thatsame number of X-decoder circuits of FIG. 1 are provided. The X-decodercircuit is configured to be connected to plural sectors. (e.g. sectorsS1, S2 in FIG. 1).

The X-decoder circuit of FIG. 1 includes a high-voltage switchingcircuit 11, a global X-decoder 12, high-voltage X-decoders 13, subX-decoders (word line drives) 14, and sector switches 15. Thehigh-voltage switching circuit 11 and the global X-decoder 12 are sharedby the plural sectors. The high-voltage X-decoder 13, plural sub Xdecoders 14, and the sector switch 15 are respectively provided in eachof the plural sectors.

FIG. 2 is a circuit diagram of the high-voltage switching circuit 11.

The high-voltage switching circuit 11 of FIG. 2 includes AND circuits 21and 22, an OR circuit 23, NMOS transistors 24 through 26, and PMOStransistors 27 through 29. A signal SELq is a signal for selecting acorresponding block, and a signal SELBq is an inversion signal of thesignal SELq. A signal ERSELVT is normally LOW (ground voltage Vss), andbecomes HIGH (supply voltage Vcc) in the erase operation. A signalERSELBVT is normally HIGH (supply voltage Vcc), and becomes LOW (groundvoltage Vss) in the erase operation. A signal SVPX becomes HIGH in theread/program operation. VPXG is an input high voltage.

The output voltage VPXq applied to a block selected for the read/programoperation is the input high voltage VPXG, because SVPX=H, SELq=H, andERSELVT=L. On the other hand, the output voltage VPXq applied to a blockunselected for the read/program operation is the ERSELBVT, becauseSVPX=H, and SELq=L. The voltage ERSELBVT is Vcc in the read operation.

The output voltage VPXq applied to a block selected for the eraseoperation is 0 V, because ERSELVT=H, and SVPX=L. On the other hand, theoutput voltage VPXq=VPXG=Vcc is applied to a block unselected for theerase operation.

FIG. 3 is a circuit diagram of the global X-decoder 12.

The global X-decoder 12 of FIG. 3 includes NAND circuits 31 and 32,inverters 33 and 34, NMOS transistors 35 and 36, and PMOS transistors 37and 38. The global X-decoder 12 applies GWLNqx=VPXq, and GWLBqx=0 V to ablock selected for the read/program operation. On the other hand, theglobal X-decoder 12 applies GWLNqx=0 V, and GWLBqx=Vcc to a blockunselected for the read/program operation. The output signals GWLNqx andGWLBqx are globally applied to the sectors. In the erase operation,VPXq=0 V, ERXTFB=0 V, and XTx=0 V, and therefore GWLNqx=0 V, andGWLBqx=0 V.

Thirty two pieces of the circuits of FIG. 3 are respectively providedfor 32 lines of GWLNq (31:0) and GWLBq (31:0). The global X-decoder 12is constituted with all these circuits (see FIG. 1). The GWLNqx andGWLBqx described above respectively correspond to single lines of GWLNq(31:0) and GWLBq (31:0).

FIG. 4 is a circuit diagram of the high-voltage X-decoder 13.

The high-voltage X-decoder 13 of FIG. 4 includes a NAND circuit 41, NMOStransistors 42 and 43, and PMOS transistors 44 and 45. The PMOStransistors 44 and 45 serve as a level shifter for converting logic inVcc level into logic in Vpx level. A signal ERXTFB becomes LOW and setsa pass gate OFF in the erase operation. A signal VXTv, which is a signalconverted from an address signal, becomes HIGH when a corresponding VWLis selected for the decoding operation. A signal SELn becomes HIGH whena sector is selected. XDS, which is a voltage signal, is normally 0 Vand becomes a negative voltage NEGP (e.g. −6 V) in the erase operation.

When the read/program operation is selected, VWLnv=VPXq. When theread/program operation is unselected, VWLnv=0 V. In the erase operation,VPXq=0 V, VXTv=SELn=H, and XDSn=NEGP, and therefore VWLnv=NEGP. Herein,NEGP is a negative voltage in the erase operation as shown in the above.

Sixteen pieces of the circuits of FIG. 4 are respectively provided for16 lines of VWLn (15:0). The high-voltage X-decoder 13 is constitutedwith all these circuits (see FIG. 1). The VWLnv of FIG. 4 describedabove corresponds to a single line of VWLn (15:0). The high-voltageX-decoder 13 is provided one for each sector.

FIG. 5 is a circuit diagram of the sub X-decoder 14.

The sub X-decoder (word line driver) 14 of FIG. 5 includes NMOStransistors 51 through 53. The sub X-decoder 14 receives VWLnv from thehigh-voltage X-decoder 13, VPXq from the high-voltage switching circuit11, GWLNqx and GWLBqx from the global X-decoder 12, and XDSn from thesector switch 15. According to these signals, the sub X-decoder 14,serving as a word line driver, drives a word line.

When a word line is selected for the read/program operation,GWLNqx=VPXq, GWLBqx=0 V, and VWLnv=VPXq. Therefore, a high voltage isapplied to a word line P2WLni. When a word line is selected for theerase operation, VPXq=0 V, VWLnv=XDSn=NEGP, and GWLNqx=GWLBqx=0 V.Therefore, a negative voltage NEGP is applied to the word line P2WLni.

FIG. 6 is a circuit diagram of the sector switch 15.

The sector switch 15 of FIG. 6 includes NAND circuits 61 and 62,inverters 63 and 64, NMOS transistors 65 through 71, and PMOStransistors 72 through 77. A signal ENSSW is an Enable signal for thiscircuit. A signal SELn is a sector selection signal as previouslymentioned. NEGP is a negative voltage supplied from a pump circuit. Asignal NEGPL is a negative voltage detection signal, which is switchedfrom Vcc to 0 V when the negative voltage signal NEGP falls below apredetermined negative voltage level.

An output voltage signal XDSn is a negative voltage when in a selectedsector, and is 0 V when in an unselected sector. Specifically, in theselected sector, signals AEN and NEN in the circuit are respectivelyNEGP and 0 V, and therefore the output voltage signal XDSn=NEGP. In theunselected sector, signals AEN and NEN are respectively Vcc and NEGP,and therefore XDSn=0 V.

The sector switch 15, provided one for each sector, supplies a negativevoltage for erasure to the sub X-decoders 14 when a corresponding sectoris selected for the erase operation. Thus the erase operation isexecuted in the sector.

The high-voltage switching circuit 11 shown in FIG. 2 is shared by thesectors, thereby allowing a reduction of the circuit area. The reasonthat the sharing of the high-voltage switching circuit 11 is applicableis because the word line can be selected by the decoding operation ofGWL/VWL in the read/program operation.

In contrast, the sector switch 15 shown in FIG. 6 is provided one foreach sector. The size of the sector switch 15 is large because thesector switch 15 includes a level shifter for controlling a negativevoltage to be applied to a selected sector and a decoding circuit forgenerating the signals AEN and NEN. Therefore, having the sector switch15 one for each sector is disadvantageous in that the circuit areaoccupied by the sector switches 15 increases in proportion to the numberof the sectors (an example of related art is described in U.S. Pat. No.5,995,417, also published as WO00/24002, and its Japanese translation2002-528841).

SUMMARY OF THE INVENTION

In view of the foregoing, a general object of the present invention isto provide a nonvolatile semiconductor memory device to overcome atleast one disadvantage mentioned above. A specific object of the presentinvention is to provide a nonvolatile semiconductor memory device withless circuit area occupied by a sector switch.

A nonvolatile semiconductor memory device according to the presentinvention comprises a plurality of sectors each including a memory cellarray, a plurality of word line drivers provided in each one of thesectors to drive respective word lines, sector switches provided one foreach sector, connected to the word line drivers in the correspondingsector, adapted to provide a negative voltage to be applied to the wordlines to the word line drivers when the corresponding sector is selectedfor an erase operation, and only including transistors directlyconnected to an output signal line to provide the negative voltage tothe word line drivers, and a decoding circuit shared by one or moresectors, adapted to control the sector switches to allow a sector switchin a selected sector to output the negative voltage and allow a sectorswitch in an unselected sector to output a voltage different from thenegative voltage.

The sector switches of the nonvolatile semiconductor memory device areprovided one for each sector, and the sector is selected by decodercircuits each shared by one or more sectors. A negative voltage forerasure is provided only to the selected sector. Each sector switch onlycomprises transistors directly connected to a signal output line forproviding a negative voltage, and other decoding functions are arrangedoutside the sectors as the decoder circuit shared by one or moresectors. Accordingly, the sector switch provided in the respectivesector can be formed as a small circuit only having driver transistors,thereby allowing considerable reduction of the circuit area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an X-decoder circuit;

FIG. 2 is a circuit diagram of a high-voltage switching circuit;

FIG. 3 is a circuit diagram of a global X-decoder;

FIG. 4 is a circuit diagram of a high-voltage X decoder;

FIG. 5 is a circuit diagram of a sub X-decoder;

FIG. 6 is a circuit diagram of a sector switch;

FIG. 7 is a schematic diagram of a nonvolatile semiconductor memorydevice according to the present invention;

FIG. 8 is a schematic diagram of a sector switching circuit according tothe present invention;

FIG. 9 is a circuit diagram of a sector switch;

FIG. 10 is a table showing combinations of voltage values of respectivesignals, and corresponding voltage values of an output signal XDSn ofthe sector switch;

FIG. 11 is a circuit diagram of a horizontal decoder;

FIG. 12 is a circuit diagram of a vertical decoder;

FIG. 13 is circuit diagram of another example of the sector switch; and

FIG. 14 is a table showing voltage values of respective signals, andcorresponding voltage values of the output signal XDSn of the sectorswitch.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Preferred embodiments of the present invention are described in detailbelow referring to the accompanying drawings.

FIG. 7 shows a schematic diagram of a nonvolatile semiconductor memorydevice 110 according to the present invention.

The nonvolatile semiconductor memory device 110 comprises a controlcircuit 111, an input/output buffer 112, an address latch 113, anX-decoder 114, a Y-decoder 115, a cell array 116, a data latch 117, aprogram voltage generating circuit 118, an erase voltage generatingcircuit 119, and a chip-enable/output-enable circuit 120.

The control circuit 111 receives a control signal from the outside, andfunctions as a state machine according to the control signal to controlthe operations of each element of the nonvolatile semiconductor memorydevice 110.

The input/output buffer 112 receives data from the outside and suppliesthe data to the data latch 117. The address latch 113 receives, orlatches, an address signal from the outside, and supplies the addresssignal to the X-decoder 114 and the Y-decoder 115. The X-decoder 114decodes the address supplied from the address latch 113, and activatesword lines arranged in the cell array 116 according to the decodedresult. The Y-decoder 115 decodes the address supplied from the addresslatch 113, and selectively opens and closes a Y-gate 115A according thedecoded address signal. The Y-gate 115A selectively connects bit linesof the cell array 116 to the data latch 117.

The cell array 116 comprises an array of memory cell transistors, wordlines, and bit lines, and stores data in each of the memory celltransistors. In a data read operation, data in memory cells specified bythe activated word line are read out to the bit lines. In theprogram/erase operation, the word lines and the bit lines are set topotentials appropriate for each operation, and thus charges are injectedinto or removed from the memory cells. The cell array 116 is dividedinto plural sectors, each of which has a memory cell array. The eraseoperation is executed by sector.

The data latch 117 compares the current of the data supplied from thecell array 116 specified by the Y-decoder 115 and the X-decoder 114 witha reference current to identify whether the data element is 0 or 1. Theidentification result is supplied as read-out data to the input/outputbuffer 112. A verify operation for the program/erase operation isexecuted by comparing the current of the data supplied from the cellarray 116 specified by the Y-decoder 115 and the X-decoder 114 with areference current indicated by a reference cell for program verify/eraseverify. In the programming operation, write data are stored in aregister of the data latch 117, and the word lines and the bit lines ofthe cell array 116 are set to appropriate potentials based on the data.The charges are thus injected into the memory cells.

The program voltage generating circuit 118 generates a high voltage forprogramming under the control of the control circuit 111. The highvoltage for programming is applied to the cell array 116 through theX-decoder 114, so that the data writing operation is executed based onthe write data stored in the data latch 117. The erase voltagegenerating circuit 119 generates a negative voltage for erasure underthe control of the control circuit 111. The negative voltage for erasureis applied to the cell array 116 through the X-decoder 114, so that theerase operation by sector is executed in the cell array 116.

The chip-enable/output-enable circuit 120 receives a chip-enable signal(/CE) and an output-enable signal (/OE) from an external device tocontrol the activation and inactivation of the input/output buffer 112and the cell array 116.

FIG. 8 shows a schematic diagram of a sector switching circuit accordingto the present invention.

The sector switching circuit of FIG. 8 comprises sector switches 131provided one for each sector, horizontal decoders 132 for selectingrespective horizontal sector rows, and vertical decoders 133 forselecting respective vertical sector rows. Plural sectors arehorizontally and vertically arranged in a matrix form. The sectorswitches 131 provided one for each sector are also arranged horizontallyand vertically. When a horizontal sector row and a vertical sector roware respectively selected by the horizontal decoder 132 and the verticaldecoder 133, one sector switch 131 is selected.

It should be understood that, although AENh/NENh are illustrated assignals provided to sector rows in the horizontal direction andNEGPXv/NEGPXBv as signals provided to sector rows in the verticaldirection in FIG. 8, the signals in the horizontal and verticaldirections may be replaced with each other. Also, all the horizontaldecoders 132 and the vertical decoders 133 may be arranged in one of thehorizontal or vertical direction to allow the decoding from the samedirection.

The configuration of the above-described related art is applicable tothe present invention except for the sector switching circuit, andtherefore the circuits shown in FIGS. 2 through 5 may be employed forthe X-decoding operation. That is, the present invention employs thesector switches 131 provided in the respective sectors in place of thesector switches 15 provided in the respective sectors in FIG. 1.

FIG. 9 shows a circuit diagram of the sector switch 131.

The sector switch 131 comprises NMOS transistors 141 through 143. Thesignals AENh/NENh are provided to a horizontal sector row by thehorizontal decoder 132. The signals NEGPXv/NEGPVBv are provided to avertical sector row by the vertical decoder 133.

FIG. 10 is a table showing combinations of voltage values of the signalsAENh/NENh and NEGPXv/NEGPXBv, and corresponding voltage values of anoutput signal XDSn of the sector switch 131. The signals AENh/NENh areNEGP/Vss in the selected state and Vcc/NEGP in the unselected state. Thesignals NEGPXv/NEGPXBv are NEGP/NEGP in the selected state and Vss/Vccin the unselected state. As shown in FIG. 10, when the signals AENh/NENhare NEGP/Vss and the signals NEGPXv/NEGPXBv are NEGP/NEGP, acorresponding sector is selected for the erase operation and the outputsignal XDSn becomes a negative voltage NEGP.

As described above, the sector switches 131 are small circuits eachcomprising three transistors only. Therefore, the circuit area isconsiderably reduced in comparison with the related art shown in FIG. 1where the circuit of FIG. 6 is provided for each sector.

FIG. 11 shows a circuit diagram of the horizontal decoder 132.

The horizontal decoder 132 of FIG. 11 comprises NAND circuits 151 and152, inverters 153 and 154, NMOS transistors 155 through 159, and PMOStransistors 160 through 165. A signal ENSSW is an Enable signal for thiscircuit. A signal HSELh is a selection signal for selecting a horizontalsector row (FIG. 8). NEGP is a negative voltage supplied from a pumpcircuit. A signal NEGPL is a negative voltage detection signal, which isswitched from Vcc to 0 V when the negative voltage signal NEGP fallsbelow a predetermined negative voltage level.

Signals AEN and NEN are respectively NEGP and Vss when applied to aselected sector, and are respectively Vcc ad NEGP when applied to anunselected sector.

FIG. 12 is a circuit diagram of the vertical decoder 133.

The vertical decoder 133 of FIG. 12 comprises NAND circuits 171 and 172,inverters 173 and 174, NMOS transistors 175 through 181, and PMOStransistors 182 through 187. A signal ENSSW is an Enable signal for thiscircuit. A signal VSELv is a selection signal for selecting a verticalsector row (FIG. 8). NEGP is a negative voltage supplied from the pumpcircuit. The signal NEGPL is a negative voltage detection signal, whichis switched from Vcc to 0 V when the negative voltage signal NEGP fallsbelow a predetermined negative voltage level.

The signals NEGPXv/NEGPXBv are NEGP/NEGP when applied to a selectedsector, and are Vss/Vcc when applied to an unselected sector.

The voltage signals thus generated by the horizontal decoder 132 of FIG.11 and the vertical decoder 133 of FIG. 12 are provided to the sectorswitch 131, so that the sector switch 131 can provide the negativevoltage NEGP for erasure.

FIG. 13 is circuit diagram of another example of the sector switch 131.

A sector switch 131A of FIG. 13 comprises NMOS transistors 191 and 192.The signals AENh/NENh are provided to a horizontal sector row by thehorizontal decoder 132. The signal NEGPXv is provided to a verticalsector row by the vertical decoder 133.

FIG. 14 is a table showing combinations of voltage values of the signalsAENh/NENh and NEGPXv, and corresponding voltage values of the outputsignal XDSn of the sector switch 131A. The signals AENh/NENh areNEGP/Vss in the selected state and Vcc/NEGP in the unselected state. Thesignal NEGPXv is NEGP in the selected state and Vss in the unselectedstate. As shown in FIG. 14, when the signals AENh/NENh are NEGP/Vss andthe signal NEGPXv is NEGP, a corresponding sector is selected for theerase operation and the output signal XDSn becomes a negative voltageNEGP.

The sector switch 131A according to this embodiment comprises only twotransistors as previously mentioned, and therefore the circuit area isfurther reduced in comparison with the sector switch 131 of FIG. 9.However, if the signals AENh/NENh are NEGP/Vss and a correspondinghorizontal row is selected and if NEGPXV is Vss, the XDSn is put in afloating state.

As described above, the sector switch of the nonvolatile semiconductormemory device according to the present invention is provided one foreach sector, and the sector is selected by decoder circuits each sharedby one or more sectors. A negative voltage for erasure is provided onlyto the selected sector. Each sector switch only comprises transistorsdirectly connected to a signal output line for providing a negativevoltage, and other decoding functions are arranged outside the sectorsas the decoder circuit shared by one or more sectors. Accordingly, thesector switch provided in the respective sector can be formed as a smallcircuit only having driver transistors, thereby allowing considerablereduction of the circuit area.

The present invention is not limited to the specifically disclosedembodiments, and variations and modifications may be made withoutdeparting from the scope of the present invention.

1. A nonvolatile semiconductor memory device, comprising: a plurality ofsectors each including a memory cell array; a plurality of word linedrivers provided in each one of the sectors to drive respective wordlines; sector switches provided one for each sector, each sector switchbeing connected to the plural word line drivers in the correspondingsector, adapted to provide a negative voltage to be applied to the wordlines to the plural word line drivers when the corresponding sector isselected for an erase operation, and only including transistors directlyconnected to an output signal line to provide the negative voltage tothe plural word line drivers; and a decoding circuit shared by one ormore sectors, adapted to control the sector switches to allow a sectorswitch in a selected sector to output the negative voltage and allow asector switch in an unselected sector to output a voltage different fromthe negative voltage.
 2. The nonvolatile semiconductor memory device asclaimed in claim 1, wherein the sector switch is connected to a negativevoltage signal line to receive the negative voltage from the decodingcircuit, the sector switch comprising: a first transistor connectedbetween the output signal line and the different voltage; and a secondtransistor connected between the output signal line and the negativevoltage signal line.
 3. The nonvolatile semiconductor memory device asclaimed claim 1, wherein the sector switch further comprises: a thirdtransistor to connect the output signal line to the different voltagewhen the first and second transistors are closed.
 4. The nonvolatilesemiconductor memory device as claimed in claim 1, wherein the sectorsare aligned in a first direction and a second direction, and thedecoding circuit comprises: a first circuit to select one of plural rowsof the sectors aligned in the first direction; and a second circuit toselect one of plural rows of the sectors aligned in the seconddirection.
 5. The nonvolatile semiconductor memory device as claimed inclaim 4, wherein the first circuit is adapted to control opening/closingoperations of the first and second transistors, and the second circuitis adapted to control a potential of the negative voltage signal line.6. The nonvolatile semiconductor memory device as claimed in claim 4,wherein the first circuit is adapted to control opening/closingoperations of the first and second transistors, and the second circuitis adapted to control opening/closing operations of a third transistorand a potential of the negative voltage signal line.
 7. The nonvolatilesemiconductor memory device as claimed in claim 1, further comprising anX-decoder circuit to select one of the word line drivers in a programoperation and a read operation.